VerilogMSThingy
Posted on March 4, 2010, 7:55 pm UTC by neuro (about 1 year ago)Code (highlighted for Verilog)
- module ckt(btn, clk, a, b, c, d, e, f, g, an, swtch, led);
- input [3:0] btn;
- input [7:0] swtch;
- input clk;
- output a, b, c, d, e, f, g;
- output [3:0] an;
- output [7:0] led;
- reg [7:0] led;
- reg a, b, c, d, e, f, g, swstate = 0;
- reg [2:0] cstate, nstate;
- reg [3:0] an;
- always @(posedge clk)
- begin
- led=swtch;
- if (swstate==0)
- begin
- an=15;
- end
- end
- always @(swtch)
- begin
- swstate=1;
- case(swtch)
- 8'b00000000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=0; c=0; d=0; e=0; f=0; g=1;//Switch 1 is on
- end
- 8'b00010000: begin
- an[0] = 1; an[1] = 0;
- a=1; b=0; c=0; d=1; e=1; f=1; g=1;//Switch 1 is on
- end
- 8'b00100000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=0; c=1; d=0; e=0; f=1; g=0;//Switch 1 is on
- end
- 8'b00110000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=0; c=0; d=0; e=1; f=1; g=0;//Switch 1 is on
- end
- 8'b01000000: begin
- an[0] = 1; an[1] = 0;
- a=1; b=1; c=0; d=1; e=1; f=0; g=0;//Switch 1 is on
- end
- 8'b01010000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=1; c=0; d=0; e=1; f=0; g=0;//Switch 1 is on
- end
- 8'b01100000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=1; c=0; d=0; e=0; f=0; g=0;//Switch 1 is on
- end
- 8'b01110000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=0; c=0; d=1; e=1; f=1; g=1;//Switch 1 is on
- end
- 8'b10000000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=0; c=0; d=0; e=0; f=0; g=0;//Switch 1 is on
- end
- 8'b10010000: begin
- an[0] = 1; an[1] = 0;
- a=0; b=0; c=0; d=1; e=1; f=0; g=0;//Switch 1 is on
- end
- 8'b10100000: begin
- an[1] = 1;
- a=1; b=0; c=0; d=1; e=1; f=1; g=1;//Switch 1 is on
- an[0] = 0;
- a=0; b=0; c=0; d=0; e=0; f=0; g=1;//Switch 1 is on
- //an[1] = 0;
- end
- 8'b10110000: begin
- an[0] = 0; an[1] = 0;
- a=1; b=1; c=1; d=1; e=1; f=1; g=1;//Switch 1 is on
- end
- 8'b11000000: begin
- an[0] = 0; an[1] = 0;
- a=1; b=1; c=1; d=1; e=1; f=1; g=1;//Switch 1 is on
- end
- 8'b11010000: begin
- an[0] = 0; an[1] = 0;
- a=1; b=1; c=1; d=1; e=1; f=1; g=1;//Switch 1 is on
- end
- 8'b11100000: begin
- an[0] = 0; an[1] = 0;
- a=1; b=1; c=1; d=1; e=1; f=1; g=1;//Switch 1 is on
- end
- 8'b11110000: begin
- an[0] = 0; an[1] = 0; a=1; b=1; c=1; d=1; e=1; f=1; g=1;//Switch 1 is on
- end
- default: begin
- an = 15; swstate = 0;
- end
- endcase
- end
- always @(btn or cstate)
- case (btn)
- 4'b1000: nstate=3; // Button 3 pressed
- 4'b0100: nstate=2; // Button 2 pressed
- 4'b0010: nstate=1; // Button 1 pressed
- 4'b0001: nstate=0; // Button 0 pressed
- 4'b0000: nstate=cstate; // No button pressed
- default: nstate=7; // No button pressed yet or multiple
- // buttons pressed
- endcase
- always @(posedge clk)
- case (cstate)
- 3: begin // Button 3 pressed
- a=0; b=0; c=0; d=0; e=1; f=1; g=0;
- end
- 2: begin // Button 2 pressed
- a=0; b=0; c=1; d=0; e=0; f=1; g=0;
- end
- 1: begin // Button 1 pressed
- a=1; b=0; c=0; d=1; e=1; f=1; g=1;
- end
- 0: begin // Button 0 pressed
- a=0; b=0; c=0; d=0; e=0; f=0; g=1;
- end
- 7: begin // No button pressed yet or multiple buttons pressed
- a=1; b=1; c=1; d=1; e=1; f=1; g=1;
- end
- endcase
- endmodule